[PATCH] D134736: [DAG] select Cond, C, -1 --> or (sext (not Cond)), C when C is MVT::i1

[Amaury SECHET via Phabricator via llvm-commits]

deadalnix updated this revision to Diff 463338.
deadalnix added a comment.

Add a test case for this spercifically in select_const and modify cmov-promotion so that this optimization doesn't kick in.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134736/new/

https://reviews.llvm.org/D134736

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/X86/pr16031.ll
  llvm/test/CodeGen/X86/select_const.ll
  llvm/test/CodeGen/X86/zext-sext.ll

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