[PATCH] D131260: [DAG] select Cond, -1, C --> or (sext Cond), C if Cond is MVT::i1

[ChenZheng via Phabricator via llvm-commits]

shchenz accepted this revision as: shchenz.
shchenz added a comment.
This revision is now accepted and ready to land.

In D131260#3817531 <https://reviews.llvm.org/D131260#3817531>, @RKSimon wrote:

> LGTM @shchenz any more comments?

PPC part looks good!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131260/new/

https://reviews.llvm.org/D131260