[PATCH] D131260: [DAG] select Cond, -1, C --> or (sext Cond), C if Cond is MVT::i1

Simon Pilgrim via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Sep 27 02:38:19 PDT 2022


RKSimon added a comment.

LGTM @shchenz any more comments?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131260/new/

https://reviews.llvm.org/D131260



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