[PATCH] D134643: [AArch64] Add tests for selecting SMULL instruction where the operand is zero extended and the top bit value is 0

[Florian Hahn via Phabricator via llvm-commits]

fhahn added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/aarch64-smull.ll:62
+; CHECK-NEXT:    ret
+  %tmp1 = load <8 x i8>, <8 x i8>* %A
+  %tmp2 = load <8 x i16>, <8 x i16>* %B
----------------
It would make the test slightly easier to read if more descriptive names for the values would be used, e.g. `%tmp2 -> load.B`, %tmp4 -> %sext.B`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134643/new/

https://reviews.llvm.org/D134643