[PATCH] D134643: [AArch64] Add tests for selecting SMULL instruction where the operand is zero extended and the top bit value is 0

[Zain Jaffal via Phabricator via llvm-commits]

zjaffal created this revision.
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This covers the case where we can convert a zext instruction to a sext and then select smull


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134643

Files:
  llvm/test/CodeGen/AArch64/aarch64-smull.ll


Index: llvm/test/CodeGen/AArch64/aarch64-smull.ll
===================================================================
--- llvm/test/CodeGen/AArch64/aarch64-smull.ll
+++ llvm/test/CodeGen/AArch64/aarch64-smull.ll
@@ -46,6 +46,94 @@
   ret <2 x i64> %tmp5
 }
 
+define <8 x i32> @smull_zext_v8i8_v8i32(<8 x i8>* %A, <8 x i16>* %B) nounwind {
+; CHECK-LABEL: smull_zext_v8i8_v8i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr d0, [x0]
+; CHECK-NEXT:    ldr q1, [x1]
+; CHECK-NEXT:    ushll v0.8h, v0.8b, #0
+; CHECK-NEXT:    sshll v2.4s, v1.4h, #0
+; CHECK-NEXT:    sshll2 v1.4s, v1.8h, #0
+; CHECK-NEXT:    ushll2 v3.4s, v0.8h, #0
+; CHECK-NEXT:    ushll v0.4s, v0.4h, #0
+; CHECK-NEXT:    mul v1.4s, v3.4s, v1.4s
+; CHECK-NEXT:    mul v0.4s, v0.4s, v2.4s
+; CHECK-NEXT:    ret
+  %tmp1 = load <8 x i8>, <8 x i8>* %A
+  %tmp2 = load <8 x i16>, <8 x i16>* %B
+  %tmp3 = zext <8 x i8> %tmp1 to <8 x i32>
+  %tmp4 = sext <8 x i16> %tmp2 to <8 x i32>
+  %tmp5 = mul <8 x i32> %tmp3, %tmp4
+  ret <8 x i32> %tmp5
+}
+
+
+define <4 x i32> @smull_zext_v4i16_v4i32(<4 x i8>* %A, <4 x i16>* %B) nounwind {
+; CHECK-LABEL: smull_zext_v4i16_v4i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr s0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    ushll v0.8h, v0.8b, #0
+; CHECK-NEXT:    sshll v1.4s, v1.4h, #0
+; CHECK-NEXT:    ushll v0.4s, v0.4h, #0
+; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    ret
+  %tmp1 = load <4 x i8>, <4 x i8>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
+  %tmp3 = zext <4 x i8> %tmp1 to <4 x i32>
+  %tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
+  %tmp5 = mul <4 x i32> %tmp3, %tmp4
+  ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @smull_zext_v2i32_v2i64(<2 x i16>* %A, <2 x i32>* %B) nounwind {
+; CHECK-LABEL: smull_zext_v2i32_v2i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr d0, [x1]
+; CHECK-NEXT:    ldrh w8, [x0]
+; CHECK-NEXT:    ldrh w11, [x0, #2]
+; CHECK-NEXT:    sshll v0.2d, v0.2s, #0
+; CHECK-NEXT:    fmov x9, d0
+; CHECK-NEXT:    mov x10, v0.d[1]
+; CHECK-NEXT:    mul x8, x8, x9
+; CHECK-NEXT:    mul x9, x11, x10
+; CHECK-NEXT:    fmov d0, x8
+; CHECK-NEXT:    mov v0.d[1], x9
+; CHECK-NEXT:    ret
+  %tmp1 = load <2 x i16>, <2 x i16>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
+  %tmp3 = zext <2 x i16> %tmp1 to <2 x i64>
+  %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
+  %tmp5 = mul <2 x i64> %tmp3, %tmp4
+  ret <2 x i64> %tmp5
+}
+
+define <2 x i64> @smull_zext_and_v2i32_v2i64(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+; CHECK-LABEL: smull_zext_and_v2i32_v2i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr d0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    bic v0.2s, #128, lsl #24
+; CHECK-NEXT:    sshll v1.2d, v1.2s, #0
+; CHECK-NEXT:    ushll v0.2d, v0.2s, #0
+; CHECK-NEXT:    fmov x9, d1
+; CHECK-NEXT:    fmov x10, d0
+; CHECK-NEXT:    mov x8, v1.d[1]
+; CHECK-NEXT:    mov x11, v0.d[1]
+; CHECK-NEXT:    mul x9, x10, x9
+; CHECK-NEXT:    mul x8, x11, x8
+; CHECK-NEXT:    fmov d0, x9
+; CHECK-NEXT:    mov v0.d[1], x8
+; CHECK-NEXT:    ret
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp1.and = and <2 x i32> %tmp1, <i32 u0x7FFFFFFF, i32 u0x7FFFFFFF>
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
+  %tmp3 = zext <2 x i32> %tmp1.and to <2 x i64>
+  %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
+  %tmp5 = mul <2 x i64> %tmp3, %tmp4
+  ret <2 x i64> %tmp5
+}
+
 define <8 x i16> @umull_v8i8_v8i16(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ; CHECK-LABEL: umull_v8i8_v8i16:
 ; CHECK:       // %bb.0:


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