[PATCH] D131260: [DAG] select Cond, -1, C --> or (sext Cond), C if Cond is MVT::i1
Amaury SECHET via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 26 06:29:01 PDT 2022
deadalnix updated this revision to Diff 462891.
deadalnix added a comment.
Fix the latest broken test
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D131260/new/
https://reviews.llvm.org/D131260
Files:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/PowerPC/crbits.ll
llvm/test/CodeGen/PowerPC/prefer-dqform.ll
llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll
llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
llvm/test/CodeGen/X86/memcmp-optsize-x32.ll
llvm/test/CodeGen/X86/memcmp-optsize.ll
llvm/test/CodeGen/X86/memcmp-pgso-x32.ll
llvm/test/CodeGen/X86/memcmp-pgso.ll
llvm/test/CodeGen/X86/memcmp-x32.ll
llvm/test/CodeGen/X86/memcmp.ll
llvm/test/CodeGen/X86/midpoint-int.ll
llvm/test/CodeGen/X86/select.ll
llvm/test/CodeGen/X86/select_const.ll
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