[PATCH] D131260: [DAG] select Cond, -1, C --> or (sext Cond), C if Cond is MVT::i1

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:23974
+  assert(N0.getOpcode() == ISD::SETCC &&
+         "First argument must be a SetCC node!");
 
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unrelated - pre-commit this?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D131260/new/

https://reviews.llvm.org/D131260