[llvm] 4f86c5c - [RISCV] Rename RISCVScheduleB.td to RISCVScheduleZb.td. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-09-23T21:38:42-07:00
New Revision: 4f86c5cbb79d268d8a21c1d83d2d475295768792

URL: https://github.com/llvm/llvm-project/commit/4f86c5cbb79d268d8a21c1d83d2d475295768792
DIFF: https://github.com/llvm/llvm-project/commit/4f86c5cbb79d268d8a21c1d83d2d475295768792.diff

LOG: [RISCV] Rename RISCVScheduleB.td to RISCVScheduleZb.td. NFC

Added: 
    llvm/lib/Target/RISCV/RISCVScheduleZb.td

Modified: 
    llvm/lib/Target/RISCV/RISCVSchedule.td

Removed: 
    llvm/lib/Target/RISCV/RISCVScheduleB.td


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVSchedule.td b/llvm/lib/Target/RISCV/RISCVSchedule.td
index 5b273bff5f97..8544e0012a76 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedule.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedule.td
@@ -230,5 +230,5 @@ def : ReadAdvance<ReadFSqrt16, 0>;
 }
 
 // Include the scheduler resources for other instruction extensions.
-include "RISCVScheduleB.td"
+include "RISCVScheduleZb.td"
 include "RISCVScheduleV.td"

diff  --git a/llvm/lib/Target/RISCV/RISCVScheduleB.td b/llvm/lib/Target/RISCV/RISCVScheduleZb.td
similarity index 100%
rename from llvm/lib/Target/RISCV/RISCVScheduleB.td
rename to llvm/lib/Target/RISCV/RISCVScheduleZb.td