[llvm] cde3de5 - [RISCV] Remove a few remnants of Zbr I misssed.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-09-23T21:21:51-07:00
New Revision: cde3de53814ffb4a63c83eecf90b13abb23595bd

URL: https://github.com/llvm/llvm-project/commit/cde3de53814ffb4a63c83eecf90b13abb23595bd
DIFF: https://github.com/llvm/llvm-project/commit/cde3de53814ffb4a63c83eecf90b13abb23595bd.diff

LOG: [RISCV] Remove a few remnants of Zbr I misssed.

Added: 
    

Modified: 
    llvm/docs/ReleaseNotes.rst
    llvm/lib/Target/RISCV/RISCVSchedRocket.td
    llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    llvm/lib/Target/RISCV/RISCVScheduleB.td

Removed: 
    


################################################################################
diff  --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 99e1e9d23e481..c4fdabc20fc74 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -112,8 +112,8 @@ Changes to the PowerPC Backend
 Changes to the RISC-V Backend
 -----------------------------
 
-* Support for the unratified Zbe, Zbf, Zbm, Zbp, and Zbt extensions have been
-  removed.
+* Support for the unratified Zbe, Zbf, Zbm, Zbp, Zbr, and Zbt extensions have
+  been removed.
 
 Changes to the WebAssembly Backend
 ----------------------------------

diff  --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
index 9a8b5e91ba541..f39f7c71c23f9 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
@@ -244,6 +244,5 @@ defm : UnsupportedSchedZbb;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbs;
 defm : UnsupportedSchedZbkb;
-defm : UnsupportedSchedZbr;
 defm : UnsupportedSchedZfh;
 }

diff  --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index a35e9351ce865..86d77e68b3c11 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -231,6 +231,5 @@ defm : UnsupportedSchedZbb;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbs;
 defm : UnsupportedSchedZbkb;
-defm : UnsupportedSchedZbr;
 defm : UnsupportedSchedZfh;
 }

diff  --git a/llvm/lib/Target/RISCV/RISCVScheduleB.td b/llvm/lib/Target/RISCV/RISCVScheduleB.td
index ab7843874f518..b0947500fecc6 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleB.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleB.td
@@ -39,16 +39,6 @@ def WritePACK32      : SchedWrite; // packw
 def WritePACKU       : SchedWrite; // packu
 def WritePACKU32     : SchedWrite; // packuw
 
-// Zbr extension
-def WriteCRCB        : SchedWrite; // crc32.b
-def WriteCRCH        : SchedWrite; // crc32.h
-def WriteCRCW        : SchedWrite; // crc32.w
-def WriteCRCD        : SchedWrite; // crc32.d
-def WriteCRCCB       : SchedWrite; // crc32c.b
-def WriteCRCCH       : SchedWrite; // crc32c.h
-def WriteCRCCW       : SchedWrite; // crc32c.w
-def WriteCRCCD       : SchedWrite; // crc32c.d
-
 /// Define scheduler resources associated with use operands.
 
 // Zba extension
@@ -82,16 +72,6 @@ def ReadPACK32      : SchedRead; // packw
 def ReadPACKU       : SchedRead; // packu
 def ReadPACKU32     : SchedRead; // packuw
 
-// Zbr extension
-def ReadCRCB        : SchedRead; // crc32.b
-def ReadCRCH        : SchedRead; // crc32.h
-def ReadCRCW        : SchedRead; // crc32.w
-def ReadCRCD        : SchedRead; // crc32.d
-def ReadCRCCB       : SchedRead; // crc32c.b
-def ReadCRCCH       : SchedRead; // crc32c.h
-def ReadCRCCW       : SchedRead; // crc32c.w
-def ReadCRCCD       : SchedRead; // crc32c.d
-
 /// Define default scheduler resources for B.
 
 multiclass UnsupportedSchedZba {
@@ -165,25 +145,3 @@ def : ReadAdvance<ReadPACKU, 0>;
 def : ReadAdvance<ReadPACKU32, 0>;
 }
 }
-
-multiclass UnsupportedSchedZbr {
-let Unsupported = true in {
-def : WriteRes<WriteCRCB, []>;
-def : WriteRes<WriteCRCH, []>;
-def : WriteRes<WriteCRCW, []>;
-def : WriteRes<WriteCRCD, []>;
-def : WriteRes<WriteCRCCB, []>;
-def : WriteRes<WriteCRCCH, []>;
-def : WriteRes<WriteCRCCW, []>;
-def : WriteRes<WriteCRCCD, []>;
-
-def : ReadAdvance<ReadCRCB, 0>;
-def : ReadAdvance<ReadCRCH, 0>;
-def : ReadAdvance<ReadCRCW, 0>;
-def : ReadAdvance<ReadCRCD, 0>;
-def : ReadAdvance<ReadCRCCB, 0>;
-def : ReadAdvance<ReadCRCCH, 0>;
-def : ReadAdvance<ReadCRCCW, 0>;
-def : ReadAdvance<ReadCRCCD, 0>;
-}
-}