[PATCH] D134382: [RISCV] Disallow scale for scatter/gather

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Sep 21 17:23:19 PDT 2022


craig.topper added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:4441
+  // Target may not support the required addressing mode.
+  if (!TLI.isLegalScaleForGatherScatter(ScaleVal, ElemSize))
+    return false;
----------------
Since the target is required to support 1 should be skip the call for 1?


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.h:605
 
+  bool isLegalScaleForGatherScatter(uint64_t Scale, uint64_t ElemSize) const override {
+    // Scaled addressing not supported on indexed load/stores
----------------
80 columns


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134382/new/

https://reviews.llvm.org/D134382



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