[PATCH] D134382: [RISCV] Disallow scale for scatter/gather

[Philip Reames via Phabricator via llvm-commits]

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RISCV doesn't actually support a scaled form of indexed load and store.  We previously handled this by forming the scaled SDNode, and then doing custom legalization during lowering.  This patch instead adds a callback via TLI to prevent formation entirely.

This has two effects:

- First, the GEP gets expanded (and used).  Instead of the shift being created with an SDLoc of the memory operation, it has the SDLoc of the GEP instruction.  This avoids the scheduler perturbing IR order when there's no reason to.
- Second, we fix what appears to be a bug in index calculation with RV32.  The rules for GEPs require index calculation be done in particular bitwidth, and it appears the custom legalization code got this wrong for the case where index type exceeds pointer width.  (Or at least, I trust the generic GEP lowering to be correct a lot more.)

The DAGCombiner change to handle VPScatter/VPGather is technically separate, but is required to prevent a regression on those intrinsics.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134382

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
  llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll

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