[PATCH] D133491: [AArch64] Try to fold shuffle (tbl2, tbl2) to tbl4.

[Florian Hahn via Phabricator via llvm-commits]

fhahn marked 2 inline comments as done.
fhahn added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:10731
+  // constant.
+  auto IsBuildVectorWithConstantOps = [](SDValue Mask) {
+    if (Mask->getOpcode() != ISD::BUILD_VECTOR)
----------------
t.p.northover wrote:
> This doesn't appear to capture anything, so maybe consider making it a static function instead? The difference from `isExtractLowerHalfMask` in the same patch seems a bit unmotivated.
> 
> Not insisting on one style or the other (or even consistency), just making sure it's an active decision.
This is not needed any longer, because it is checked in the loop below now.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:10734
+      return false;
+    for (unsigned I = 0; I < 8; I++) {
+      if (!isa<ConstantSDNode>(Mask->getOperand(I)))
----------------
t.p.northover wrote:
> Would also need to extend this check. Or perhaps better only check the indices that are actually used by the shuffle, so move this into the main loop later.
Done in the loop below, thanks!


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D133491/new/

https://reviews.llvm.org/D133491