[PATCH] D133491: [AArch64] Try to fold shuffle (tbl2, tbl2) to tbl4.

[Florian Hahn via Phabricator via llvm-commits]

fhahn updated this revision to Diff 461877.
fhahn added a comment.



In D133491#3802133 <https://reviews.llvm.org/D133491#3802133>, @t.p.northover wrote:

>> It is quite specific but this kind of pattern can be produced by loop-vectorization, in combination with the recent changes using tbl instructions for extends/truncates.
>
> I think it's more restrictive than it needs to be, and we should drop the `isExtractLowerHalfMask` check entirely. Any constant shuffle of two constant tbl2 operations ought to be representable with a constant tbl4, and that check's only there because our index-mapping is too naive.
>
> Instead I think we want something like this in the loop where we generate the new tbl indices (now running through all 16 lanes):

Thanks Tim! Generalized as suggested.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133491/new/

https://reviews.llvm.org/D133491

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/arm64-tbl.ll
  llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll

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