[PATCH] D134019: [MachineCycle][NFC]add a cache for block and top level cycle mapping

[ChenZheng via Phabricator via llvm-commits]

shchenz marked an inline comment as done.
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In D134019#3804673 <https://reviews.llvm.org/D134019#3804673>, @avogelsgesang wrote:

> does it make sense to add a regression test?

This is a compile time improvement, no compiler functionality change. AFAIK, we don't have regression test for the compile time changes.


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D134019