[PATCH] D133491: [AArch64] Try to fold shuffle (tbl2, tbl2) to tbl4.

[Tim Northover via Phabricator via llvm-commits]

t.p.northover added a comment.

> It is quite specific but this kind of pattern can be produced by loop-vectorization, in combination with the recent changes using tbl instructions for extends/truncates.

I think it's more restrictive than it needs to be, and we should drop the `isExtractLowerHalfMask` check entirely. Any constant shuffle of two constant tbl2 operations ought to be representable with a constant tbl4, and that check's only there because our index-mapping is too naive.

Instead I think we want something like this in the loop where we generate the new tbl indices (now running through all 16 lanes):

  if (ShuffleMask[I] < 16)
    TblMaskParts[I] = Mask1->getOperand(ShuffleMask[I]);
  else {
    auto *C = cast<ConstantSDNode>(Mask2->getOperand(ShuffleMask[I] - 16));
    TblMaskParts[I] = DAG.getConstant(C->getSExtValue() + 32, dl, MVT::i32);
  }



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:10731
+  // constant.
+  auto IsBuildVectorWithConstantOps = [](SDValue Mask) {
+    if (Mask->getOpcode() != ISD::BUILD_VECTOR)
----------------
This doesn't appear to capture anything, so maybe consider making it a static function instead? The difference from `isExtractLowerHalfMask` in the same patch seems a bit unmotivated.

Not insisting on one style or the other (or even consistency), just making sure it's an active decision.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D133491/new/

https://reviews.llvm.org/D133491