[PATCH] D134263: [llvm][dwarf] A unique CIE for all FDEs with same initial frame instructions

[Juan Manuel Martinez Caamaño via Phabricator via llvm-commits]

jmmartinez created this revision.
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Currently while emitting Dwarf debug frame section data, unique CIE entries are
generated only when frames have different exception handling characteristics.

This proves to be inefficient in terms of space consumed by FDE entries when
multiple frames have same default CFI instructions on entry to those frames as
we will be generating all those same CFI instructions into each FDE entry.

This patch makes it possible to create a unique CIE entry for all the frames
having the same initial CFI instructions on entry to those frames thus saving
space consumed by those FDE entries.

A new place holder is introduced to hold this information as the existing
MCAsmInfo::InitialFrameState cannot represent the per frame (function) specific
initial instructions.

Fixes: SWDEV-205726

Change-Id: I832681e8d454b7ed50f133091c367af22a42125a


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134263

Files:
  llvm/include/llvm/CodeGen/MachineFunction.h
  llvm/include/llvm/MC/MCDwarf.h
  llvm/include/llvm/MC/MCStreamer.h
  llvm/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp
  llvm/lib/MC/MCAsmStreamer.cpp
  llvm/lib/MC/MCDwarf.cpp
  llvm/lib/MC/MCStreamer.cpp
  llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
  llvm/lib/Target/AMDGPU/SIFrameLowering.h
  llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
  llvm/test/CodeGen/AMDGPU/amdgpu-spill-cfi-saved-regs.ll
  llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
  llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir
  llvm/test/CodeGen/AMDGPU/debug-frame.ll
  llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
  llvm/test/CodeGen/AMDGPU/frame-index.mir
  llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
  llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
  llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir
  llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
  llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir
  llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir
  llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir
  llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
  llvm/test/CodeGen/AMDGPU/prologue-epilogue-markers.ll
  llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll
  llvm/test/CodeGen/AMDGPU/returnaddress_cfi.ll
  llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir
  llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
  llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
  llvm/test/CodeGen/AMDGPU/spill-agpr.mir
  llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
  llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir
  llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll
  llvm/test/CodeGen/AMDGPU/unique-CIE-for-FDEs-with-same-initial-frame-instructions.ll
  llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
  llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
  llvm/test/DebugInfo/AMDGPU/cfi.ll