[PATCH] D134078: [AMDGPU] Fix useDeprecatedPositionallyEncodedOperands errors in R600.

[James Y Knight via Phabricator via llvm-commits]

jyknight created this revision.
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This is a follow-on to https://reviews.llvm.org/D134073.

It renames a couple of fields to match their operands, as well as
introducing sub-operand names where required.

This change _only_ fixes the 'R600' half of the target, not the
'AMDGPU' half. Fixing the AMDGPU half will be a significantly more
difficult change (which I've not yet attempted.)


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134078

Files:
  llvm/lib/Target/AMDGPU/R600.td
  llvm/lib/Target/AMDGPU/R600Instructions.td


Index: llvm/lib/Target/AMDGPU/R600Instructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/R600Instructions.td
+++ llvm/lib/Target/AMDGPU/R600Instructions.td
@@ -641,16 +641,16 @@
 def FETCH_CLAUSE : R600WrapperInst <(outs),
 (ins i32imm:$addr), "Fetch clause starting at $addr:", [] > {
   field bits<8> Inst;
-  bits<8> num;
-  let Inst = num;
+  bits<8> addr;
+  let Inst = addr;
   let isCodeGenOnly = 1;
 }
 
 def ALU_CLAUSE : R600WrapperInst <(outs),
 (ins i32imm:$addr), "ALU clause starting at $addr:", [] > {
   field bits<8> Inst;
-  bits<8> num;
-  let Inst = num;
+  bits<8> addr;
+  let Inst = addr;
   let isCodeGenOnly = 1;
 }
 
@@ -1452,8 +1452,8 @@
 } // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"
 
 def TEX_VTX_CONSTBUF :
-  InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$buffer_id), "VTX_READ_eg $dst, $ptr",
-      [(set v4i32:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr, (i32 imm:$buffer_id)))]>,
+  InstR600ISA <(outs R600_Reg128:$dst_gpr), (ins (MEMxi $src_gpr, $src_index):$src, i32imm:$buffer_id), "VTX_READ_eg $dst_gpr, $src",
+      [(set v4i32:$dst_gpr, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$src, (i32 imm:$buffer_id)))]>,
   VTX_WORD1_GPR, VTX_WORD0_eg {
 
   let VC_INST = 0;
@@ -1506,7 +1506,7 @@
 }
 
 def TEX_VTX_TEXBUF:
-  InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$buffer_id), "TEX_VTX_EXPLICIT_READ $dst, $ptr">,
+  InstR600ISA <(outs R600_Reg128:$dst_gpr), (ins (MEMxi $src_gpr, $src_index):$src, i32imm:$buffer_id), "TEX_VTX_EXPLICIT_READ $dst_gpr, $src">,
 VTX_WORD1_GPR, VTX_WORD0_eg {
 
 let VC_INST = 0;
Index: llvm/lib/Target/AMDGPU/R600.td
===================================================================
--- llvm/lib/Target/AMDGPU/R600.td
+++ llvm/lib/Target/AMDGPU/R600.td
@@ -10,8 +10,6 @@
 
 def R600InstrInfo : InstrInfo {
   let guessInstructionProperties = 1;
-  let noNamedPositionallyEncodedOperands = 1;
-  let useDeprecatedPositionallyEncodedOperands = 1;
 }
 
 def R600 : Target {


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