[PATCH] D76883: [AMDGPU] Implement CFI for CSR spills

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp:217
+      const TargetRegisterClass *RC =
+          TRI->getMinimalPhysRegClass(RetAddrReg, MVT::i64);
+      int JunkFI = MFI.CreateStackObject(TRI->getSpillSize(*RC),
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Should avoid using getMinimalPhysRegClass, should just hardcode a 64-bit scalar class


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76883/new/

https://reviews.llvm.org/D76883