[llvm] 8bb5c89 - [AMDGPU][MC][NFC] Refactor AMDGPUAsmParser::validateVOPLiteral

[Dmitry Preobrazhensky via llvm-commits]

Author: Dmitry Preobrazhensky
Date: 2022-09-15T16:26:14+03:00
New Revision: 8bb5c8920581c403ad60265e44bfa7417891ec8d

URL: https://github.com/llvm/llvm-project/commit/8bb5c8920581c403ad60265e44bfa7417891ec8d
DIFF: https://github.com/llvm/llvm-project/commit/8bb5c8920581c403ad60265e44bfa7417891ec8d.diff

LOG: [AMDGPU][MC][NFC] Refactor AMDGPUAsmParser::validateVOPLiteral

Differential Revision: https://reviews.llvm.org/D133861

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index cbf2f1bf8f33a..a0412be408346 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1662,6 +1662,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
   bool validateVccOperand(unsigned Reg) const;
   bool validateVOPLiteral(const MCInst &Inst, const OperandVector &Operands);
   bool validateMAIAccWrite(const MCInst &Inst, const OperandVector &Operands);
+  bool validateMAISrc2(const MCInst &Inst, const OperandVector &Operands);
   bool validateMFMA(const MCInst &Inst, const OperandVector &Operands);
   bool validateAGPRLdSt(const MCInst &Inst) const;
   bool validateVGPRAlign(const MCInst &Inst) const;
@@ -3807,6 +3808,28 @@ bool AMDGPUAsmParser::validateMAIAccWrite(const MCInst &Inst,
   return true;
 }
 
+bool AMDGPUAsmParser::validateMAISrc2(const MCInst &Inst,
+                                      const OperandVector &Operands) {
+  unsigned Opcode = Inst.getOpcode();
+  const MCInstrDesc &Desc = MII.get(Opcode);
+
+  if (!(Desc.TSFlags & SIInstrFlags::IsMAI) ||
+      !getFeatureBits()[FeatureMFMAInlineLiteralBug])
+    return true;
+
+  const int Src2Idx = getNamedOperandIdx(Opcode, OpName::src2);
+  if (Src2Idx == -1)
+    return true;
+
+  if (Inst.getOperand(Src2Idx).isImm() && isInlineConstant(Inst, Src2Idx)) {
+    Error(getConstLoc(Operands),
+          "inline constants are not allowed for this operand");
+    return false;
+  }
+
+  return true;
+}
+
 bool AMDGPUAsmParser::validateMFMA(const MCInst &Inst,
                                    const OperandVector &Operands) {
   const unsigned Opc = Inst.getOpcode();
@@ -4287,13 +4310,6 @@ bool AMDGPUAsmParser::validateVOPLiteral(const MCInst &Inst,
     if (!AMDGPU::isSISrcOperand(Desc, OpIdx))
       continue;
 
-    if (OpIdx == Src2Idx && (Desc.TSFlags & SIInstrFlags::IsMAI) &&
-        getFeatureBits()[AMDGPU::FeatureMFMAInlineLiteralBug]) {
-      Error(getConstLoc(Operands),
-            "inline constants are not allowed for this operand");
-      return false;
-    }
-
     if (MO.isImm() && !isInlineConstant(Inst, OpIdx)) {
       uint32_t Value = static_cast<uint32_t>(MO.getImm());
       if (NumLiterals == 0 || LiteralValue != Value) {
@@ -4645,6 +4661,9 @@ bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
   if (!validateMAIAccWrite(Inst, Operands)) {
     return false;
   }
+  if (!validateMAISrc2(Inst, Operands)) {
+    return false;
+  }
   if (!validateMFMA(Inst, Operands)) {
     return false;
   }