[PATCH] D132942: [PowerPC][GISel]add support for float point arithmetic operations

Wed Sep 14 21:36:39 PDT 2022

amyk added inline comments.

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Comment at: llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp:40-42
+  case PPC::SPILLTOVSRRC_and_VSFRCRegClassID:
+  case PPC::SPILLTOVSRRC_and_VFRCRegClassID:
+  case PPC::SPILLTOVSRRC_and_F4RCRegClassID:
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shchenz wrote:
> nemanjai wrote:
> > Why are these classes included? Is it expected that global isel works with `-ppc-enable-gpr-to-vsr-spills`?
> This is from the auto-generated td file `PPCGenRegisterBank.inc` for register bank `FPRRegBankID`. This function should be TableGen'ed.
A question that I thought of and was curious about is regarding these register classes and the test cases you added.

Are those tests only corresponding to a single/certain register classes out of the ones you added? Should we be testing all types of register classes in the tests (if that is even possible)?

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Comment at: llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td:16
 def GPRRegBank : RegisterBank<"GPR", [G8RC, G8RC_NOX0]>;
+/// Float point Registers
+def FPRRegBank : RegisterBank<"FPR", [VSSRC]>;
----------------
nit: Floating point Registers.

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Comment at: llvm/test/CodeGen/PowerPC/GlobalISel/float-arithmetic.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel -o - < %s | FileCheck %s
+
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I was thinking it might be good to include `-ppc-vsr-nums-as-vr -ppc-asm-full-reg-names` like we do in our other test cases.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D132942/new/

https://reviews.llvm.org/D132942