[PATCH] D133869: [RISCV] Verify SEW/VecPolicy immediate values

[Philip Reames via Phabricator via llvm-commits]

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Copy the asserts from the printing code, and turn them into actual verifier rules.  Doing this revealed an existing bug - see D133868 <https://reviews.llvm.org/D133868>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D133869

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp


Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1220,6 +1220,25 @@
     }
   }
 
+  const uint64_t TSFlags = Desc.TSFlags;
+  if (RISCVII::hasSEWOp(TSFlags)) {
+    unsigned OpIdx = RISCVII::getSEWOpNum(MI.getDesc());
+    unsigned Log2SEW = MI.getOperand(OpIdx).getImm();
+    unsigned SEW = Log2SEW ? 1 << Log2SEW : 8;
+    if (!RISCVVType::isValidSEW(SEW)) {
+      ErrInfo = "Unexpected SEW value";
+      return false;
+    }
+  }
+  if (RISCVII::hasVecPolicyOp(TSFlags)) {
+    unsigned OpIdx = RISCVII::getVecPolicyOpNum(MI.getDesc());
+    unsigned Policy = MI.getOperand(OpIdx).getImm();
+    if (Policy > (RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC)) {
+      ErrInfo = "Invalid Policy Value";
+      return false;
+    }
+  }
+
   return true;
 }
 


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