[PATCH] D131389: [AArch64] Add Missing v8.8a ALLINT PSTATE

[Peter Smith via Phabricator via llvm-commits]

peter.smith added a comment.

A reference I found helpful when looking at this in revision ia of the Arm ARM (https://developer.arm.com/documentation/ddi0487/ia/?lang=en) `Instructions for accessing the PSTATE fields`

  CFINV ; Inverts the value of PSTATE.C
  MSR DAIFSet, #Imm4 ; Used to set any or all of DAIF to 1
  MSR DAIFClr, #Imm4 ; Used to clear any or all of DAIF to 0
  MSR SPSel, #Imm4 ; Used to select the Stack Pointer, between SP_EL0 and SP_ELx
  MSR UAO, #Imm4 ; Used to set the value of PSTATE.UAO
  MSR PAN, #Imm4 ; Used to set the value of PSTATE.PAN
  MSR DIT, #Imm4 ; Used to set the value of PSTATE.DIT
  MSR SSBS, #Imm4 ; Used to set the value of PSTATE.SSBS
  MSR TCO, #Imm4 ; Used to set the value of PSTATE.TCO
  MSR ALLINT, #Imm1 ; Used to set the value of PSTATE.ALLINT

I think the disassembler changes to decode the field as 4-bits looks fine. Changing the assembler to accept 4-bit fields for the fields that are logically on or off, while closer to the architecture, makes it possible to write assembler that isn't going to assemble on the GNU assembler which only accepts 0 or 1. I think that if we change we should at least inform GNU of the change. Personally I don't think that any human will choose to use anything other than 0 or 1 so I don't necessarily think this is going to be a problem in practice.

Hope I've understood that correctly.


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