[PATCH] D133184: AMDGPU: Factor out hasDivergentBranch(). NFC

[Ruiling, Song via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0404aafbe3dd: AMDGPU: Factor out hasDivergentBranch(). NFC (authored by ruiling).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133184/new/

https://reviews.llvm.org/D133184

Files:
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp


Index: llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
+++ llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
@@ -124,6 +124,7 @@
 ///
 class PhiIncomingAnalysis {
   MachinePostDominatorTree &PDT;
+  const SIInstrInfo *TII;
 
   // For each reachable basic block, whether it is a source in the induced
   // subgraph of the CFG.
@@ -133,7 +134,8 @@
   SmallVector<MachineBasicBlock *, 4> Predecessors;
 
 public:
-  PhiIncomingAnalysis(MachinePostDominatorTree &PDT) : PDT(PDT) {}
+  PhiIncomingAnalysis(MachinePostDominatorTree &PDT, const SIInstrInfo *TII)
+      : PDT(PDT), TII(TII) {}
 
   /// Returns whether \p MBB is a source in the induced subgraph of reachable
   /// blocks.
@@ -166,18 +168,7 @@
 
       // If this block has a divergent terminator and the def block is its
       // post-dominator, the wave may first visit the other successors.
-      bool Divergent = false;
-      for (MachineInstr &MI : MBB->terminators()) {
-        if (MI.getOpcode() == AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO ||
-            MI.getOpcode() == AMDGPU::SI_IF ||
-            MI.getOpcode() == AMDGPU::SI_ELSE ||
-            MI.getOpcode() == AMDGPU::SI_LOOP) {
-          Divergent = true;
-          break;
-        }
-      }
-
-      if (Divergent && PDT.dominates(&DefBlock, MBB))
+      if (TII->hasDivergentBranch(MBB) && PDT.dominates(&DefBlock, MBB))
         append_range(Stack, MBB->successors());
     }
 
@@ -541,7 +532,7 @@
 bool SILowerI1Copies::lowerPhis() {
   MachineSSAUpdater SSAUpdater(*MF);
   LoopFinder LF(*DT, *PDT);
-  PhiIncomingAnalysis PIA(*PDT);
+  PhiIncomingAnalysis PIA(*PDT, TII);
   SmallVector<MachineInstr *, 4> Vreg1Phis;
   SmallVector<MachineBasicBlock *, 4> IncomingBlocks;
   SmallVector<unsigned, 4> IncomingRegs;
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.h
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -277,6 +277,10 @@
 
   MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
 
+  /// Return whether the block terminate with divergent branch.
+  /// Note this only work before lowering the pseudo control flow instructions.
+  bool hasDivergentBranch(const MachineBasicBlock *MBB) const;
+
   void insertIndirectBranch(MachineBasicBlock &MBB,
                             MachineBasicBlock &NewDestBB,
                             MachineBasicBlock &RestoreBB, const DebugLoc &DL,
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -2379,6 +2379,16 @@
   return MI.getOperand(0).getMBB();
 }
 
+bool SIInstrInfo::hasDivergentBranch(const MachineBasicBlock *MBB) const {
+  for (const MachineInstr &MI : MBB->terminators()) {
+    if (MI.getOpcode() == AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO ||
+        MI.getOpcode() == AMDGPU::SI_IF || MI.getOpcode() == AMDGPU::SI_ELSE ||
+        MI.getOpcode() == AMDGPU::SI_LOOP)
+      return true;
+  }
+  return false;
+}
+
 void SIInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
                                        MachineBasicBlock &DestBB,
                                        MachineBasicBlock &RestoreBB,


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