[llvm] 7886505 - llvm-reduce: Add undef to new subregister IMPLICIT_DEFs

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2022-09-13T18:10:56-04:00
New Revision: 78865050620e6b6b90be7e868ffe5d5e67159856

URL: https://github.com/llvm/llvm-project/commit/78865050620e6b6b90be7e868ffe5d5e67159856
DIFF: https://github.com/llvm/llvm-project/commit/78865050620e6b6b90be7e868ffe5d5e67159856.diff

LOG: llvm-reduce: Add undef to new subregister IMPLICIT_DEFs

This avoids a verifier error from the other unused lanes when
LiveIntervals is used.

Added: 
    

Modified: 
    llvm/test/tools/llvm-reduce/mir/subreg-def0.mir
    llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/test/tools/llvm-reduce/mir/subreg-def0.mir b/llvm/test/tools/llvm-reduce/mir/subreg-def0.mir
index 590ea6155a573..dd3ecd7385e16 100644
--- a/llvm/test/tools/llvm-reduce/mir/subreg-def0.mir
+++ b/llvm/test/tools/llvm-reduce/mir/subreg-def0.mir
@@ -5,7 +5,7 @@
 # CHECK-INTERESTINGNESS: V_ADD_U32
 
 # RESULT: undef %{{[0-9]+}}.sub1:vreg_64 = IMPLICIT_DEF
-# RESULT-NEXT: %{{[0-9]+}}.sub0:vreg_64 = IMPLICIT_DEF
+# RESULT-NEXT: undef %{{[0-9]+}}.sub0:vreg_64 = IMPLICIT_DEF
 # RESULT-NEXT: %1:vgpr_32 = V_ADD_U32_e32 %{{[0-9]+}}.sub0, %{{[0-9]+}}.sub1, implicit $exec
 # RESULT-NEXT: S_ENDPGM 0, implicit %1
 

diff  --git a/llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp b/llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
index c87d5eb9a44f2..9b2a4759026ea 100644
--- a/llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
+++ b/llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
@@ -128,8 +128,13 @@ static void extractInstrFromFunction(Oracle &O, MachineFunction &MF) {
         bool IsGeneric = MRI->getRegClassOrNull(Reg) == nullptr;
         unsigned ImpDef = IsGeneric ? TargetOpcode::G_IMPLICIT_DEF
                                     : TargetOpcode::IMPLICIT_DEF;
+
+        unsigned State = getRegState(MO);
+        if (MO.getSubReg())
+          State |= RegState::Undef;
+
         BuildMI(*EntryMBB, EntryInsPt, DebugLoc(), TII->get(ImpDef))
-          .addReg(NewReg, getRegState(MO), MO.getSubReg());
+          .addReg(NewReg, State, MO.getSubReg());
       }
 
       // Update all uses.