[PATCH] D133810: [RISCV\ Verify consistency of a couple TSFlags related to vector operands

[Philip Reames via Phabricator via llvm-commits]

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Mostly a starting point for discussion.  I think it makes sense to have verification rules for these flags; mostly to make it easier to figure out their function.  Do others agree?

If so, any other proposed rules we'd like to enforce?  I picked these two somewhat arbitrarily based on code I was looking at today.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D133810

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp


Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1220,6 +1220,15 @@
     }
   }
 
+  uint64_t TSFlags = MI.getDesc().TSFlags;
+  if (RISCVII::hasVLOp(TSFlags) && !RISCVII::hasSEWOp(TSFlags)) {
+    ErrInfo = "VL operand w/o SEW operand?";
+    return false;
+  }
+  if (RISCVII::hasVecPolicyOp(TSFlags) && !RISCVII::hasVLOp(TSFlags)) {
+    ErrInfo = "policy operand w/o SEW operand?";
+    return false;
+  }
   return true;
 }
 


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