[PATCH] D133572: [MachinePipeliner] Fix the interpretation of the scheduling model

Tue Sep 13 08:20:45 PDT 2022

dpenry accepted this revision.
dpenry added a comment.
This revision is now accepted and ready to land.

LGTM

In D133572#3786257 <https://reviews.llvm.org/D133572#3786257>, @ytmukai wrote:

> 

<snip>

> Thumb2 tests passed by disabling the restriction of issue width. (I had forgotten that the ARM swp tests are under Thumb2.)

That's fine for now; I may tweak them in a new patch to ensure they're still adequately testing what they were intended to test.

> Regarding problem on getting scheduling classes, I understand that the interface resolveSchedClass should be used, but the problem spans the entire code and I would like to solve it in a separate patch, is that ok?

Sure.  Let's make it soon, though.  IIRC, when I was doing my changes, not resolving the class led to occasionally odd results for Cortex-M7.

> Thanks for the info about unbuffered groups. I have not yet understood the details and have addressed it in a future patch if necessary.

Yeah, this all gets pretty hairy.   Look at https://reviews.llvm.org/D98976 for a thread with me trying to figure out what it all means once there are resource groups in play.

Repository:
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https://reviews.llvm.org/D133572