[PATCH] D133572: [MachinePipeliner] Fix the interpretation of the scheduling model

[Yuta Mukai via Phabricator via llvm-commits]

ytmukai marked 3 inline comments as done.
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@dpenry Thank you for the reviews!

Thumb2 tests passed by disabling the restriction of issue width. (I had forgotten that the ARM swp tests are under Thumb2.)

The number of issues per cycle was changed to be counted in micro-ops. Micro-ops are assumed to be scheduled one per cycle, starting with the cycle in which the instruction is scheduled. (Reserved at `reserveResources()`) This may differ from actual operation, but it prevents an instruction from being unschedulable if it has a large number of micro-ops relative to the issue width. In MachineScheduler, when the number of micro-ops exceeds the limit, it seems that a next cycle's slot is used. In any case, the model does not have that much resolution, so I preferred a simple implementation.

Regarding problem on getting scheduling classes, I understand that the interface resolveSchedClass should be used, but the problem spans the entire code and I would like to solve it in a separate patch, is that ok?

Thanks for the info about unbuffered groups. I have not yet understood the details and have addressed it in a future patch if necessary.


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https://reviews.llvm.org/D133572