[PATCH] D133688: [RISCV] Lower BUILD_VECTOR to RISCVISD::VID_VL if it is floating-point type.

Mon Sep 12 11:45:52 PDT 2022

craig.topper added a comment.

In D133688#3784547 <https://reviews.llvm.org/D133688#3784547>, @reames wrote:

> High level question - why approach this as checking to see if the float is representable as an integer instead of just using the bit-pattern of the float?  Using the bit-pattern would seem to match the vid sequence with a large base offset.  If so, we could either emit the base as a constant, or leverage the float to int conversion if within the sequence is in the representable range.

I didn't follow this. Doesn't normalization of the mantissa make the exponents varied so they wouldn't be linear?

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Comment at: llvm/test/CodeGen/RISCV/rvv/vle_vid-vfwcvt.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s
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The title of this test says vfwcvt, but there are no vfwcvt instructions generated.

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https://reviews.llvm.org/D133688