[PATCH] D133708: [LegalizeTypes][NVPTX] Remove extra compare from fallback code for ISD::ADD in ExpandIntRes_ADDSUB.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, arsenm, spatel, efriedma.
Herald added subscribers: mattd, gchakrabarti, asavonic, StephenFan, hiraditya.
Herald added a project: All.
craig.topper requested review of this revision.
Herald added subscribers: wdng, jholewinski.
Herald added a project: LLVM.

This is the ultimate fallback code if UADDO isn't supported.

If the target uses 0/1 we used one compare, but if the target doesn't
use 0/1 we emitted two compares. Regardless of boolean constants we
should only need to check that the Result is less than one of the
original operands. So we only need one compare.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D133708

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/test/CodeGen/NVPTX/add-sub-128bit.ll


Index: llvm/test/CodeGen/NVPTX/add-sub-128bit.ll
===================================================================
--- llvm/test/CodeGen/NVPTX/add-sub-128bit.ll
+++ llvm/test/CodeGen/NVPTX/add-sub-128bit.ll
@@ -7,10 +7,9 @@
 ; COMMON-LABEL: test_add
 define i128 @test_add(i128 %a, i128 %b) {
 ; NOCARRY:        add.s64
-; NOCARRY-NEXT:   setp.lt.u64
+; NOCARRY-NEXT:   add.s64
 ; NOCARRY-NEXT:   setp.lt.u64
 ; NOCARRY-NEXT:   selp.u64
-; NOCARRY-NEXT:   selp.b64
 ; NOCARRY-NEXT:   add.s64
 
 ; CARRY:          add.cc.s64
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -2988,23 +2988,17 @@
   if (N->getOpcode() == ISD::ADD) {
     Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
     Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
-    SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
-                                ISD::SETULT);
+    SDValue Cmp = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
+                               ISD::SETULT);
 
-    if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent) {
-      SDValue Carry = DAG.getZExtOrTrunc(Cmp1, dl, NVT);
-      Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry);
-      return;
-    }
+    SDValue Carry;
+    if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent)
+      Carry = DAG.getZExtOrTrunc(Cmp, dl, NVT);
+    else
+      Carry = DAG.getSelect(dl, NVT, Cmp, DAG.getConstant(1, dl, NVT),
+                             DAG.getConstant(0, dl, NVT));
 
-    SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
-                                   DAG.getConstant(1, dl, NVT),
-                                   DAG.getConstant(0, dl, NVT));
-    SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
-                                ISD::SETULT);
-    SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
-                                   DAG.getConstant(1, dl, NVT), Carry1);
-    Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
+    Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry);
   } else {
     Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
     Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));


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