[PATCH] D133580: [VPlan] Only generate single instr for unpredicated stores of varying value to invariant address

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


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Comment at: llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll:1088
 ; TF-FIXEDLEN-NEXT:    [[TMP1:%.*]] = add i64 [[INDEX]], 1
-; TF-FIXEDLEN-NEXT:    store i64 [[TMP0]], ptr [[B:%.*]], align 8
-; TF-FIXEDLEN-NEXT:    store i64 [[TMP1]], ptr [[B]], align 8
+; TF-FIXEDLEN-NEXT:    store i64 [[TMP1]], ptr [[B:%.*]], align 8
 ; TF-FIXEDLEN-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[TMP0]]
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This diff confused me at first since it seems to involve tail folding - which would involve predication.  However, it looks like this is a case where an existing vectorizer bug causes a loop to be vectorized with a scalar epilogue even when the command line says to tail fold or don't vectorize.  So, this isn't actually tail folded codegen.  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133580/new/

https://reviews.llvm.org/D133580