[PATCH] D133464: [WIP][BPF] Add sext load instructions

[Alexei Starovoitov via Phabricator via llvm-commits]

ast added inline comments.


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Comment at: llvm/lib/Target/BPF/BPFInstrInfo.td:469
+  def LDHS : LOADi64<BPF_H, BPF_MEM_SEXT, "s16", sextloadi16>;
+  def LDBS : LOADi64<BPF_B, BPF_MEM_SEXT, "s8",  sextloadi8>;
 }
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I believe x86 and arm64 have instructions that sign extends one register into another,
but not insns that sign extend during the load.
Such insns can be composed better to in case s32 came as a return value from a call.
Have you considered going that route?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133464/new/

https://reviews.llvm.org/D133464