[PATCH] D133408: [LegalizeTypes][LegalizeDAG] Use misaligned load/store to optimize memory access with non-power2 integer types.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Do we have test coverage for load+store patterns involving integers larger than 56 bits?

If the code quality issues are specific to 56 bits, it might make sense to make the initial patch skip handling 56-bit integers, and try to address them in a followup.



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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:815
                           LD->getPointerInfo().getWithOffset(IncrementSize),
-                          ExtraVT, LD->getOriginalAlign(), MMOFlags, AAInfo);
+                          ExtraVT, ExtraAlign, MMOFlags, AAInfo);
 
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The alignment on this load isn't right.

The "alignment" of a load SDNode isn't the alignment of the load itself; it's the alignment of the base of the MachinePointerInfo.  So if you're using getWithOffset() to adjust the MachinePointerInfo, the alignment doesn't change based on the offset.  (This distinction helps make alias analysis more accurate.)


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133408/new/

https://reviews.llvm.org/D133408