[PATCH] D133019: [VPlan] Only generate single instr for loads uniform across all parts.

[Florian Hahn via Phabricator via llvm-commits]

fhahn added inline comments.


================
Comment at: llvm/lib/Transforms/Vectorize/LoopVectorize.cpp:9659
                                       State);
+      if (!UI->getType()->isVoidTy())
+        for (unsigned Part = 1; Part < State.UF; ++Part)
----------------
reames wrote:
> A load can't be of void type.  
Done in the committed version, thanks!  I'll submit a follow-up to extend this to instructions other than loads.


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Comment at: llvm/lib/Transforms/Vectorize/LoopVectorize.cpp:9663
+                    VPIteration(Part, 0));
+    } else {
+      // Uniform within VL means we need to generate lane 0 only for each
----------------
reames wrote:
> Please use early turn instead of else clause.
Done in the committed version, thanks!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133019/new/

https://reviews.llvm.org/D133019