[PATCH] D133019: [VPlan] Only generate single instr for loads uniform across all parts.

[Florian Hahn via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
fhahn marked 2 inline comments as done.
Closed by commit rG422cf99161ed: [VPlan] Only generate single instr for loads uniform across all parts. (authored by fhahn).

Changed prior to commit:
  https://reviews.llvm.org/D133019?vs=456952&id=458716#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133019/new/

https://reviews.llvm.org/D133019

Files:
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
  llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
  llvm/test/Transforms/LoopVectorize/X86/cost-model-assert.ll
  llvm/test/Transforms/LoopVectorize/X86/uniform_mem_op.ll
  llvm/test/Transforms/LoopVectorize/induction.ll
  llvm/test/Transforms/LoopVectorize/pointer-select-runtime-checks.ll

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