[llvm] c37acb6 - [Hexagon] Move vectorization checks from subtarget to TTI
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 7 14:54:11 PDT 2022
Author: Krzysztof Parzyszek
Date: 2022-09-07T14:47:24-07:00
New Revision: c37acb642660d83b83390d768ad7a12573a876ae
URL: https://github.com/llvm/llvm-project/commit/c37acb642660d83b83390d768ad7a12573a876ae
DIFF: https://github.com/llvm/llvm-project/commit/c37acb642660d83b83390d768ad7a12573a876ae.diff
LOG: [Hexagon] Move vectorization checks from subtarget to TTI
Added:
Modified:
llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
index 2283d1b7f9c68..357354d177f20 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -75,11 +75,6 @@ static cl::opt<bool> EnableCheckBankConflict(
"hexagon-check-bank-conflict", cl::Hidden, cl::init(true),
cl::desc("Enable checking for cache bank conflicts"));
-static cl::opt<bool> EnableV68FloatCodeGen(
- "force-hvx-float", cl::Hidden,
- cl::desc(
- "Enable the code-generation for vector float instructions on v68."));
-
HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
StringRef FS, const TargetMachine &TM)
: HexagonGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
@@ -149,19 +144,8 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
std::string FeatureString = Features.getString();
ParseSubtargetFeatures(CPUString, /*TuneCPU*/ CPUString, FeatureString);
- // Enable float code generation only if the flag(s) are set and
- // the feature is enabled. v68 is guarded by additional flags.
- bool GreaterThanV68 = false;
- if (useHVXV69Ops())
- GreaterThanV68 = true;
-
- // Support for deprecated qfloat/ieee codegen flags
- if (!GreaterThanV68) {
- if (EnableV68FloatCodeGen)
- UseHVXFloatingPoint = true;
- } else {
- UseHVXFloatingPoint = true;
- }
+ if (useHVXV68Ops())
+ UseHVXFloatingPoint = UseHVXIEEEFPOps || UseHVXQFloatOps;
if (UseHVXQFloatOps && UseHVXIEEEFPOps && UseHVXFloatingPoint)
LLVM_DEBUG(
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
index 0a7a4b0fe733d..779577816fb93 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
@@ -29,14 +29,18 @@ using namespace llvm;
#define DEBUG_TYPE "hexagontti"
static cl::opt<bool> HexagonAutoHVX("hexagon-autohvx", cl::init(false),
- cl::Hidden, cl::desc("Enable loop vectorizer for HVX"));
+ cl::Hidden, cl::desc("Enable loop vectorizer for HVX"));
+
+static cl::opt<bool> EnableV68FloatAutoHVX(
+ "force-hvx-float", cl::Hidden,
+ cl::desc("Enable auto-vectorization of floatint point types on v68."));
static cl::opt<bool> EmitLookupTables("hexagon-emit-lookup-tables",
- cl::init(true), cl::Hidden,
- cl::desc("Control lookup table emission on Hexagon target"));
+ cl::init(true), cl::Hidden,
+ cl::desc("Control lookup table emission on Hexagon target"));
static cl::opt<bool> HexagonMaskedVMem("hexagon-masked-vmem", cl::init(true),
- cl::Hidden, cl::desc("Enable masked loads/stores for HVX"));
+ cl::Hidden, cl::desc("Enable masked loads/stores for HVX"));
// Constant "cost factor" to make floating point operations more expensive
// in terms of vectorization cost. This isn't the best way, but it should
@@ -47,6 +51,17 @@ bool HexagonTTIImpl::useHVX() const {
return ST.useHVXOps() && HexagonAutoHVX;
}
+bool HexagonTTIImpl::isHVXVectorType(Type *Ty) const {
+ auto *VecTy = dyn_cast<VectorType>(Ty);
+ if (!VecTy)
+ return false;
+ if (!ST.isTypeForHVX(VecTy))
+ return false;
+ if (ST.useHVXV69Ops() || !VecTy->getElementType()->isFloatingPointTy())
+ return true;
+ return ST.useHVXV68Ops() && EnableV68FloatAutoHVX;
+}
+
unsigned HexagonTTIImpl::getTypeNumElements(Type *Ty) const {
if (auto *VTy = dyn_cast<FixedVectorType>(Ty))
return VTy->getNumElements();
@@ -175,7 +190,7 @@ InstructionCost HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
if (Src->isVectorTy()) {
VectorType *VecTy = cast<VectorType>(Src);
unsigned VecWidth = VecTy->getPrimitiveSizeInBits().getFixedSize();
- if (useHVX() && ST.isTypeForHVX(VecTy)) {
+ if (isHVXVectorType(VecTy)) {
unsigned RegWidth =
getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector)
.getFixedSize();
@@ -256,6 +271,8 @@ InstructionCost HexagonTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
TTI::TargetCostKind CostKind,
const Instruction *I) {
if (ValTy->isVectorTy() && CostKind == TTI::TCK_RecipThroughput) {
+ if (!isHVXVectorType(ValTy) && ValTy->isFPOrFPVectorTy())
+ return InstructionCost::getMax();
std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(ValTy);
if (Opcode == Instruction::FCmp)
return LT.first + FloatFactor * getTypeNumElements(ValTy);
@@ -274,6 +291,8 @@ InstructionCost HexagonTTIImpl::getArithmeticInstrCost(
Op2Info, Args, CxtI);
if (Ty->isVectorTy()) {
+ if (!isHVXVectorType(Ty) && Ty->isFPOrFPVectorTy())
+ return InstructionCost::getMax();
std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty);
if (LT.second.isFloatingPoint())
return LT.first + FloatFactor * getTypeNumElements(Ty);
@@ -287,6 +306,12 @@ InstructionCost HexagonTTIImpl::getCastInstrCost(unsigned Opcode, Type *DstTy,
TTI::CastContextHint CCH,
TTI::TargetCostKind CostKind,
const Instruction *I) {
+ auto isNonHVXFP = [this] (Type *Ty) {
+ return Ty->isVectorTy() && !isHVXVectorType(Ty) && Ty->isFPOrFPVectorTy();
+ };
+ if (isNonHVXFP(SrcTy) || isNonHVXFP(DstTy))
+ return InstructionCost::getMax();
+
if (SrcTy->isFPOrFPVectorTy() || DstTy->isFPOrFPVectorTy()) {
unsigned SrcN = SrcTy->isFPOrFPVectorTy() ? getTypeNumElements(SrcTy) : 0;
unsigned DstN = DstTy->isFPOrFPVectorTy() ? getTypeNumElements(DstTy) : 0;
@@ -323,10 +348,14 @@ InstructionCost HexagonTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
}
bool HexagonTTIImpl::isLegalMaskedStore(Type *DataType, Align /*Alignment*/) {
+ // This function is called from scalarize-masked-mem-intrin, which runs
+ // in pre-isel. Use ST directly instead of calling isHVXVectorType.
return HexagonMaskedVMem && ST.isTypeForHVX(DataType);
}
bool HexagonTTIImpl::isLegalMaskedLoad(Type *DataType, Align /*Alignment*/) {
+ // This function is called from scalarize-masked-mem-intrin, which runs
+ // in pre-isel. Use ST directly instead of calling isHVXVectorType.
return HexagonMaskedVMem && ST.isTypeForHVX(DataType);
}
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
index 8d5a4edff9173..98d315c8fcde8 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
@@ -43,6 +43,7 @@ class HexagonTTIImpl : public BasicTTIImplBase<HexagonTTIImpl> {
const HexagonTargetLowering *getTLI() const { return &TLI; }
bool useHVX() const;
+ bool isHVXVectorType(Type *Ty) const;
// Returns the number of vector elements of Ty, if Ty is a vector type,
// or 1 if Ty is a scalar type. It is incorrect to call this function
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