[PATCH] D133408: [AArch64] Use misaligned load/store to optimize memory access with non-power2 integer types.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:800
+      if (TLI.allowMisalignedMemForNonPow2Type(SrcVT, LD->getAddressSpace(),
+                                               ExtraLoadAlign, MMOFlags)) {
+        IncSizeBits = ExtraWidth;
----------------
The alignment you're passing in here doesn't seem right; you want to pass in the alignment of the load you're planning to generate, right?


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:2045
 
+bool AArch64TargetLowering::allowMisalignedMemForNonPow2Type(
+    EVT VT, unsigned AddrSpace, Align Alignment,
----------------
None of this logic looks like it's target-specific; can we just do this in target-independent code?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133408/new/

https://reviews.llvm.org/D133408