[PATCH] D133408: [AArch64] Use misaligned load/store to optimize memory access with non-power2 integer types.

[chenglin.bi via Phabricator via llvm-commits]

bcl5980 updated this revision to Diff 458409.
bcl5980 added a comment.

fix test failed.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133408/new/

https://reviews.llvm.org/D133408

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/test/CodeGen/AArch64/arm64-non-pow2-ldst.ll

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