[PATCH] D133437: [AMDGPU][MC][GFX11] Add disassembler tests for v_readfirstlane_b32

[Dmitry Preobrazhensky via Phabricator via llvm-commits]

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These tests are formally not valid because this instruction may be promoted to `VOP3` and so `VOP1` variant should have `_e32` suffix when disassembled. But we do not support `VOP3` variant of this instruction yet (and maybe never will).


https://reviews.llvm.org/D133437

Files:
  llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt


Index: llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt
===================================================================
--- llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt
+++ llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt
@@ -2650,6 +2650,24 @@
 # GFX11: v_rcp_iflag_f32_e32 v255, 0xaf123456    ; encoding: [0xff,0x56,0xfe,0x7f,0x56,0x34,0x12,0xaf]
 0xff,0x56,0xfe,0x7f,0x56,0x34,0x12,0xaf
 
+# GFX11: v_readfirstlane_b32 s5, v1              ; encoding: [0x01,0x05,0x0a,0x7e]
+0x01,0x05,0x0a,0x7e
+
+# GFX11: v_readfirstlane_b32 s105, v1            ; encoding: [0x01,0x05,0xd2,0x7e]
+0x01,0x05,0xd2,0x7e
+
+# GFX11: v_readfirstlane_b32 vcc_lo, v1          ; encoding: [0x01,0x05,0xd4,0x7e]
+0x01,0x05,0xd4,0x7e
+
+# GFX11: v_readfirstlane_b32 vcc_hi, v1          ; encoding: [0x01,0x05,0xd6,0x7e]
+0x01,0x05,0xd6,0x7e
+
+# GFX11: v_readfirstlane_b32 ttmp15, v1          ; encoding: [0x01,0x05,0xf6,0x7e]
+0x01,0x05,0xf6,0x7e
+
+# GFX11: v_readfirstlane_b32 null, v255          ; encoding: [0xff,0x05,0xf8,0x7e]
+0xff,0x05,0xf8,0x7e
+
 # GFX11: v_rndne_f16_e32 v5, v1                  ; encoding: [0x01,0xbd,0x0a,0x7e]
 0x01,0xbd,0x0a,0x7e
 


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