[PATCH] D133399: [DAGCombiner] Fold (mul (sra X, BW-1), Y) -> (neg (and (sra X, BW-1), Y))
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 7 08:35:16 PDT 2022
craig.topper added inline comments.
================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:3953
+ SelectionDAG &DAG) {
+ if (N0.getOpcode() != ISD::SRA)
+ return SDValue();
----------------
RKSimon wrote:
> Would this work more generally if we tested for NumSignBits == BitWidth instead?
It’s starts picking up vectors of constants if we do that and it wasn’t clear that the test changes were improvements.
I can add a TODO?
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rG LLVM Github Monorepo
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https://reviews.llvm.org/D133399/new/
https://reviews.llvm.org/D133399
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