[PATCH] D133399: [DAGCombiner] Fold (mul (sra X, BW-1), Y) -> (neg (and (sra X, BW-1), Y))

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:3953
+                                  SelectionDAG &DAG) {
+  if (N0.getOpcode() != ISD::SRA)
+    return SDValue();
----------------
Would this work more generally if we tested for NumSignBits == BitWidth instead?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D133399/new/

https://reviews.llvm.org/D133399