[PATCH] D131786: [ARM] Support all versions of AND, ORR, EOR and BIC in optimizeCompareInstr

[Filipp Zhinkin via Phabricator via llvm-commits]

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Supported shifts


fzhinkin added a comment.

Added tests on zero comparison for equality.


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Rebase


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Built stage2 binaries and executed clang and llvm tests, all passed: F24440281: build.log.bz2 <https://reviews.llvm.org/F24440281>


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Rebase



================
Comment at: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp:3009
   case ARM::t2LSLri:
   case ARM::t2LSLrr:
     return true;
----------------
Didn't support shifts as it seems very unlikely to see these instructions here.


================
Comment at: llvm/test/CodeGen/ARM/cmp-peephole.ll:6
+
+define i1 @cmp_ne_zero_and_rr(i32 %a, i32 %b) {
+; ARM-LABEL: cmp_ne_zero_and_rr:
----------------
I'll precommit new tests if there will be no objections.


Combine cmp with zero and all versions of AND, ORR, EOR and BIC instructions into S-suffixed versions.

Related issue: https://github.com/llvm/llvm-project/issues/57122


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D131786

Files:
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/lib/Target/ARM/ARMInstrInfo.td
  llvm/test/CodeGen/ARM/branch-on-zero.ll
  llvm/test/CodeGen/ARM/cmp-peephole.ll
  llvm/test/CodeGen/ARM/consthoist-icmpimm.ll
  llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
  llvm/test/CodeGen/ARM/icmp-shift-opt.ll
  llvm/test/CodeGen/ARM/sadd_sat.ll
  llvm/test/CodeGen/ARM/sadd_sat_plus.ll
  llvm/test/CodeGen/ARM/sat-to-bitop.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll
  llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll

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