[PATCH] D133063: [docs] Add a RISC-V Usage page

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/docs/RISCVUsage.rst:78
+``Zve32x``, ``Zve32f``, ``Zvl32b``
+  LLVM currently assumes a minimum VLEN (vector register width) of 64 bits during compilation, and as a result ``Zve32x`` and ``Zve32f`` are supported only for VLEN>=64.  Assembly tools (e.g. assembler, dissambler, llvm-objdump, etc..) don't have this restriction.
+
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dissambler -> disassembler


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  https://reviews.llvm.org/D133063/new/

https://reviews.llvm.org/D133063