[llvm] 4658366 - [ARM64EC 3/?] Mark reserved registers specific to ARM64EC ABI.
Eli Friedman via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 5 13:00:37 PDT 2022
Author: Eli Friedman
Date: 2022-09-05T12:59:39-07:00
New Revision: 4658366d95d5e398baad956225cc4ba339d5b037
URL: https://github.com/llvm/llvm-project/commit/4658366d95d5e398baad956225cc4ba339d5b037
DIFF: https://github.com/llvm/llvm-project/commit/4658366d95d5e398baad956225cc4ba339d5b037.diff
LOG: [ARM64EC 3/?] Mark reserved registers specific to ARM64EC ABI.
Part of patchset to add initial support for ARM64EC.
I'm not completely sure I understand the reason for this restriction,
but Microsoft documentation says that asynchronous signals clobber these
registers, so we can't ever use them.
As far as I know, none of these registers have any hardcoded meaning, so
reserving them shouldn't have any significant side-effects.
Differental Revision: https://reviews.llvm.org/D125413
Added:
llvm/test/CodeGen/AArch64/arm64ec-reservedregs.ll
Modified:
llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/utils/UpdateTestChecks/asm.py
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index a761a1a37ee7f..7a0c7d013dd0d 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -320,6 +320,18 @@ AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
if (TFI->hasFP(MF) || TT.isOSDarwin())
markSuperRegs(Reserved, AArch64::W29);
+ if (MF.getSubtarget<AArch64Subtarget>().isWindowsArm64EC()) {
+ // x13, x14, x23, x24, x28, and v16-v31 are clobbered by asynchronous
+ // signals, so we can't ever use them.
+ markSuperRegs(Reserved, AArch64::W13);
+ markSuperRegs(Reserved, AArch64::W14);
+ markSuperRegs(Reserved, AArch64::W23);
+ markSuperRegs(Reserved, AArch64::W24);
+ markSuperRegs(Reserved, AArch64::W28);
+ for (unsigned i = AArch64::B16; i <= AArch64::B31; ++i)
+ markSuperRegs(Reserved, i);
+ }
+
for (size_t i = 0; i < AArch64::GPR32commonRegClass.getNumRegs(); ++i) {
if (MF.getSubtarget<AArch64Subtarget>().isXRegisterReserved(i))
markSuperRegs(Reserved, AArch64::GPR32commonRegClass.getRegister(i));
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index c92e3e44de317..31315953be3b9 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -245,6 +245,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
+ bool isWindowsArm64EC() const { return TargetTriple.isWindowsArm64EC(); }
bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
diff --git a/llvm/test/CodeGen/AArch64/arm64ec-reservedregs.ll b/llvm/test/CodeGen/AArch64/arm64ec-reservedregs.ll
new file mode 100644
index 0000000000000..c28f78a237939
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/arm64ec-reservedregs.ll
@@ -0,0 +1,98 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=arm64ec-pc-windows-msvc < %s | FileCheck %s
+
+; Make sure we're reserving all the registers that are supposed to be
+; reserved. Integer regs x13, x15, x23, x24, x28. Float regs v16-v31.
+; We confirm this by ensuring that we spill if and only if none of the
+; unreserved registers are available.
+
+define i32 @no_int_regs(i32 %x) nounwind {
+; CHECK-LABEL: no_int_regs:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: stp x30, x29, [sp, #-80]! // 16-byte Folded Spill
+; CHECK-NEXT: str x27, [sp, #16] // 8-byte Folded Spill
+; CHECK-NEXT: stp x26, x25, [sp, #32] // 16-byte Folded Spill
+; CHECK-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill
+; CHECK-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
+; CHECK-NEXT: str w0, [sp, #28] // 4-byte Folded Spill
+; CHECK-NEXT: //APP
+; CHECK-NEXT: //NO_APP
+; CHECK-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
+; CHECK-NEXT: ldp x26, x25, [sp, #32] // 16-byte Folded Reload
+; CHECK-NEXT: ldr w0, [sp, #28] // 4-byte Folded Reload
+; CHECK-NEXT: ldr x27, [sp, #16] // 8-byte Folded Reload
+; CHECK-NEXT: ldp x30, x29, [sp], #80 // 16-byte Folded Reload
+; CHECK-NEXT: ret
+entry:
+ tail call void asm sideeffect "", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x15},~{x16},~{x17},~{x19},~{x20},~{x21},~{x22},~{x25},~{x26},~{x27},~{fp},~{lr}"()
+ ret i32 %x
+}
+
+define i32 @one_int_reg(i32 %x) nounwind {
+; CHECK-LABEL: one_int_reg:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: stp x30, x29, [sp, #-80]! // 16-byte Folded Spill
+; CHECK-NEXT: str x27, [sp, #16] // 8-byte Folded Spill
+; CHECK-NEXT: mov w30, w0
+; CHECK-NEXT: stp x26, x25, [sp, #32] // 16-byte Folded Spill
+; CHECK-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill
+; CHECK-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
+; CHECK-NEXT: //APP
+; CHECK-NEXT: //NO_APP
+; CHECK-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-NEXT: mov w0, w30
+; CHECK-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
+; CHECK-NEXT: ldp x26, x25, [sp, #32] // 16-byte Folded Reload
+; CHECK-NEXT: ldr x27, [sp, #16] // 8-byte Folded Reload
+; CHECK-NEXT: ldp x30, x29, [sp], #80 // 16-byte Folded Reload
+; CHECK-NEXT: ret
+entry:
+ tail call void asm sideeffect "", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x15},~{x16},~{x17},~{x19},~{x20},~{x21},~{x22},~{x25},~{x26},~{x27},~{fp}"()
+ ret i32 %x
+}
+
+define float @no_float_regs(float %x) nounwind {
+; CHECK-LABEL: no_float_regs:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sub sp, sp, #80
+; CHECK-NEXT: stp d15, d14, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT: stp d13, d12, [sp, #32] // 16-byte Folded Spill
+; CHECK-NEXT: stp d11, d10, [sp, #48] // 16-byte Folded Spill
+; CHECK-NEXT: stp d9, d8, [sp, #64] // 16-byte Folded Spill
+; CHECK-NEXT: str s0, [sp, #12] // 4-byte Folded Spill
+; CHECK-NEXT: //APP
+; CHECK-NEXT: //NO_APP
+; CHECK-NEXT: ldp d9, d8, [sp, #64] // 16-byte Folded Reload
+; CHECK-NEXT: ldp d11, d10, [sp, #48] // 16-byte Folded Reload
+; CHECK-NEXT: ldp d13, d12, [sp, #32] // 16-byte Folded Reload
+; CHECK-NEXT: ldp d15, d14, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT: ldr s0, [sp, #12] // 4-byte Folded Reload
+; CHECK-NEXT: add sp, sp, #80
+; CHECK-NEXT: ret
+entry:
+ tail call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15}"()
+ ret float %x
+}
+
+define float @one_float_reg(float %x) nounwind {
+; CHECK-LABEL: one_float_reg:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: stp d15, d14, [sp, #-64]! // 16-byte Folded Spill
+; CHECK-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT: fmov s15, s0
+; CHECK-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill
+; CHECK-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill
+; CHECK-NEXT: //APP
+; CHECK-NEXT: //NO_APP
+; CHECK-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload
+; CHECK-NEXT: fmov s0, s15
+; CHECK-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload
+; CHECK-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT: ldp d15, d14, [sp], #64 // 16-byte Folded Reload
+; CHECK-NEXT: ret
+entry:
+ tail call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14}"()
+ ret float %x
+}
+
diff --git a/llvm/utils/UpdateTestChecks/asm.py b/llvm/utils/UpdateTestChecks/asm.py
index 1366e10e92e26..3bf1244b0bb19 100644
--- a/llvm/utils/UpdateTestChecks/asm.py
+++ b/llvm/utils/UpdateTestChecks/asm.py
@@ -467,6 +467,7 @@ def get_run_handler(triple):
'arm': (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_RE),
'arm64': (scrub_asm_arm_eabi, ASM_FUNCTION_AARCH64_RE),
'arm64e': (scrub_asm_arm_eabi, ASM_FUNCTION_AARCH64_DARWIN_RE),
+ 'arm64ec': (scrub_asm_arm_eabi, ASM_FUNCTION_AARCH64_RE),
'arm64-apple-ios': (scrub_asm_arm_eabi, ASM_FUNCTION_AARCH64_DARWIN_RE),
'armv7-apple-ios' : (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_IOS_RE),
'armv7-apple-darwin': (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_DARWIN_RE),
More information about the llvm-commits
mailing list