[PATCH] D133282: [TargetLowering][X86][AMDGPU] Teach expandMUL_LOHI to handle a mix of sign and zero extend.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D133282#3770947 <https://reviews.llvm.org/D133282#3770947>, @spatel wrote:

> Should we have a generic combine instead?
>
> If we have something like this - https://alive2.llvm.org/ce/z/NAmVa3 - then it's always better to get rid of the mul unless we have 'minsize':
>
>   define i32 @src(i32 %x, i32 %y) {
>     %ysign = ashr i32 %y, 31
>     %m = mul i32 %x, %ysign
>     ret i32 %m
>   }
>   
>   define i32 @tgt(i32 %x, i32 %y) {
>     %isneg = icmp slt i32 %y, 0
>     %negx = sub i32 0, %x
>     %m = select i1 %isneg, i32 %negx, i32 0
>     ret i32 %m
>   }
>
>
>
>   % llc -o - mul.ll -mtriple=riscv32 -mattr=m
>   	srai	a1, a1, 31
>   	mul	a0, a0, a1
>   ...
>   	neg	a0, a0
>   	srai	a1, a1, 31
>   	and	a0, a1, a0
>   
>   % llc -o - mul.ll -mtriple=aarch64         
>   	asr	w8, w1, #31
>   	mul	w0, w0, w8
>   ...
>   	neg	w8, w0
>   	and	w0, w8, w1, asr #31
>   
>   % llc -o - mul.ll -mtriple=x86_64 
>   	movl	%esi, %eax
>   	sarl	$31, %eax
>   	imull	%edi, %eax
>   ...
>   	movl	%esi, %eax
>   	negl	%edi
>   	sarl	$31, %eax
>   	andl	%edi, %eax

Would we do a second combine for (add Z, (and X, (neg Y)) to get the (sub Z, (and X, Y))?


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