[PATCH] D133198: [SCCP] convert signed div/rem to unsigned for non-negative operands

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In D133198#3769266 <https://reviews.llvm.org/D133198#3769266>, @bcl5980 wrote:

> Should we do this in Instcombine also? Like check Known.isNonNegative() for LHS and RHS in instcombine?
> SCCP can work on the cases with dominated condition. And Instcombine with value tracking also help the case like abs or and a mask without sign bits?

It's already done:
https://github.com/llvm/llvm-project/blob/8534f514747d57cd42602403eb98c8230f5c7ff9/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp#L1218
https://github.com/llvm/llvm-project/blob/8534f514747d57cd42602403eb98c8230f5c7ff9/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp#L1607

We miss the transform in the motivating case because the dominating condition is converted to select. So we could also match select patterns in instcombine, but I like this as a more general solution.


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https://reviews.llvm.org/D133198