[PATCH] D133198: [SCCP] convert signed div/rem to unsigned for non-negative operands

[chenglin.bi via Phabricator via llvm-commits]

bcl5980 added a comment.

Should we do this in Instcombine also? Like check Known.isNonNegative() for LHS and RHS in instcombine?
SCCP can work on the cases with dominated condition. And Instcombine with value tracking also help the case like abs or and a mask without sign bits?


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  https://reviews.llvm.org/D133198/new/

https://reviews.llvm.org/D133198