[PATCH] D133063: [docs] Add a RISC-V Usage page

Philip Reames via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Sep 2 08:59:02 PDT 2022


reames added a comment.

In D133063#3767071 <https://reviews.llvm.org/D133063#3767071>, @tschuett wrote:

> Are you going make a distinction between support on trunk and shipped with LLVM15?

Docs always follow a release branch with the default being ToT.  So, effectively LLVM 15 will not have this page, LLVM 16 will.

If you have specific extensions where documenting support isn't available in the 15 release, point them out.  We might add text on a case by case basis.



================
Comment at: llvm/docs/RISCVUsage.rst:18
+
+The specification defines three base instruction sets: RV32I, RV64I, and RV128I.
+Currently, LLVM supports RV32I, and RV64I, but not RV128I.
----------------
kito-cheng wrote:
> reames wrote:
> > asb wrote:
> > > I think RV32E is typically described as a base instruction set too (albeit one that is actually a subset of RV32I).
> > Do we support RV32E?  You're right that this seems to be a base instruction set.  If we do support it, how do we name that argument wise?
> > 
> > For now, I updated the text to indicate we didn't support RV32E, but I'm unsure if this is correct.
> RV32E is supported in MC-layer[1] but not CodeGen[2], and we have RV64E ISA[2] now, that should be worth to mention that we are not support that here.
> 
> [1] https://reviews.llvm.org/D59470
> [2] https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/RISCV/RISCVISelLowering.cpp#L53
> [2] https://github.com/riscv/riscv-isa-manual/commit/b5f94a845760af00ff2743dd9f2269fd68236576
I'll add in the RV32E bit - thanks for the links.

I'm not going to add RV64E as that's not yet in a ratified version of the specification.  We can consider adding it under experimental once we have in tree code for it.  


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