[llvm] 77dbc52 - [MachineCSE] Use TargetInstrInfo::isAsCheapAsAMove in isPRECandidate.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-08-31T15:39:41-07:00
New Revision: 77dbc5200bb5bf8fbf42d6f183599c2ae9575f29

URL: https://github.com/llvm/llvm-project/commit/77dbc5200bb5bf8fbf42d6f183599c2ae9575f29
DIFF: https://github.com/llvm/llvm-project/commit/77dbc5200bb5bf8fbf42d6f183599c2ae9575f29.diff

LOG: [MachineCSE] Use TargetInstrInfo::isAsCheapAsAMove in isPRECandidate.

Some targets like RISC-V require operands to be inspected to
determine if an instruction is similar to a move.

Spotted while investigating code differences between using an ADDI
vs an ADDIW. RISC-V has the isAsCheapAsAMove flag for ADDI, but
the TII hook checks the immediate is 0 or the register is X0. ADDIW
is never generated with X0 or with an immediate of 0 so it doesn't
have the isAsCheapAsAMove flag.

I don't know enough about the PRE code to write a test for this yet.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D132981

Added: 
    

Modified: 
    llvm/lib/CodeGen/MachineCSE.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp
index c6756b1d3737..da2fd66b43c9 100644
--- a/llvm/lib/CodeGen/MachineCSE.cpp
+++ b/llvm/lib/CodeGen/MachineCSE.cpp
@@ -789,7 +789,7 @@ bool MachineCSE::isPRECandidate(MachineInstr *MI) {
   if (!isCSECandidate(MI) ||
       MI->isNotDuplicable() ||
       MI->mayLoad() ||
-      MI->isAsCheapAsAMove() ||
+      TII->isAsCheapAsAMove(*MI) ||
       MI->getNumDefs() != 1 ||
       MI->getNumExplicitDefs() != 1)
     return false;