[PATCH] D133213: [LLVM][AArch64] Explain that X19 is used as the frame base pointer register

[David Spickett via Phabricator via llvm-commits]

DavidSpickett created this revision.
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Fixes #50098

LLVM uses X19 as the frame base pointer, if it needs to. Meaning you
can get warnings if you clobber that with inline asm.

However, it doesn't explain why. The frame base register is not part
of the ABI so it's pretty confusing why you get that warning out of the blue.

This adds a method to explain a reserved register with X19 as the first one.
The logic is the same as getReservedRegs.

I could have added a return parameter to isASMClobberable and friends
but found that there's a lot of things that call isReservedReg in various
ways.

So while one more method on the pile isn't great design, it is simpler
right now to do it this way and only pay the cost if you are actually using
a reserved register.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D133213

Files:
  llvm/include/llvm/CodeGen/TargetRegisterInfo.h
  llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
  llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
  llvm/lib/Target/AArch64/AArch64RegisterInfo.h
  llvm/test/CodeGen/AArch64/inline-asm-clobber-base-frame-pointer.ll


Index: llvm/test/CodeGen/AArch64/inline-asm-clobber-base-frame-pointer.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/inline-asm-clobber-base-frame-pointer.ll
@@ -0,0 +1,11 @@
+; RUN: llc <%s -mtriple=aarch64-none-eabi 2>&1 | FileCheck %s
+
+; CHECK: warning: inline asm clobber list contains reserved registers: X19
+; CHECK: note: X16 is used as the frame base pointer register.
+
+define dso_local void @alloca(i64 %size, i8* %base) {
+entryz:
+  %a = alloca i128, i64 %size, align 64
+  call void asm sideeffect "nop", "~{x19}"()
+  ret void
+}
\ No newline at end of file
Index: llvm/lib/Target/AArch64/AArch64RegisterInfo.h
===================================================================
--- llvm/lib/Target/AArch64/AArch64RegisterInfo.h
+++ llvm/lib/Target/AArch64/AArch64RegisterInfo.h
@@ -89,6 +89,8 @@
   const uint32_t *getWindowsStackProbePreservedMask() const;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
+  const char *explainReservedReg(const MachineFunction &MF,
+                                 MCRegister PhysReg) const override;
   bool isAsmClobberable(const MachineFunction &MF,
                        MCRegister PhysReg) const override;
   const TargetRegisterClass *
Index: llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -308,6 +308,15 @@
   return CSR_AArch64_StackProbe_Windows_RegMask;
 }
 
+const char *AArch64RegisterInfo::explainReservedReg(const MachineFunction &MF,
+                                                    MCRegister PhysReg) const {
+  if (hasBasePointer(MF) &&
+      (PhysReg == AArch64::X19 || PhysReg == AArch64::W19))
+    return "X16 is used as the frame base pointer register.";
+
+  return nullptr;
+}
+
 BitVector
 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   const AArch64FrameLowering *TFI = getFrameLowering(MF);
Index: llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
===================================================================
--- llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
+++ llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
@@ -411,6 +411,13 @@
         LocCookie, Msg, DiagnosticSeverity::DS_Warning));
     MMI->getModule()->getContext().diagnose(
         DiagnosticInfoInlineAsm(LocCookie, Note, DiagnosticSeverity::DS_Note));
+
+    for (const Register RR: RestrRegs) {
+      if (const char* reason = TRI->explainReservedReg(*MF, RR)) {
+        MMI->getModule()->getContext().diagnose(
+            DiagnosticInfoInlineAsm(LocCookie, reason, DiagnosticSeverity::DS_Note));
+      }
+    }
   }
 
   emitInlineAsm(OS.str(), getSubtargetInfo(), TM.Options.MCOptions, LocMD,
Index: llvm/include/llvm/CodeGen/TargetRegisterInfo.h
===================================================================
--- llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -523,6 +523,13 @@
   /// markSuperRegs() and checkAllSuperRegsMarked() in this case.
   virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
 
+  /// Returns either nullptr or a non null pointer to a string explaining
+  /// why the given register is reserved for the given machine function.
+  virtual const char *explainReservedReg(const MachineFunction &MF,
+                                         MCRegister PhysReg) const {
+    return nullptr;
+  }
+
   /// Returns false if we can't guarantee that Physreg, specified as an IR asm
   /// clobber constraint, will be preserved across the statement.
   virtual bool isAsmClobberable(const MachineFunction &MF,


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