[llvm] c29c617 - [SCCP][PhaseOrdering] add tests for sdiv/srem range transforms; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 1 13:23:10 PDT 2022
Author: Sanjay Patel
Date: 2022-09-01T16:23:00-04:00
New Revision: c29c6170fd0a530978806ff944da5313782366b6
URL: https://github.com/llvm/llvm-project/commit/c29c6170fd0a530978806ff944da5313782366b6
DIFF: https://github.com/llvm/llvm-project/commit/c29c6170fd0a530978806ff944da5313782366b6.diff
LOG: [SCCP][PhaseOrdering] add tests for sdiv/srem range transforms; NFC
issue #57472
Added:
llvm/test/Transforms/PhaseOrdering/srem.ll
llvm/test/Transforms/SCCP/divrem.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/Transforms/PhaseOrdering/srem.ll b/llvm/test/Transforms/PhaseOrdering/srem.ll
new file mode 100644
index 0000000000000..fd935c6f86861
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/srem.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -O1 -S < %s | FileCheck %s
+; RUN: opt -O2 -S < %s | FileCheck %s
+; RUN: opt -O3 -S < %s | FileCheck %s
+
+define i32 @PR57472(i32 noundef %x) {
+; CHECK-LABEL: @PR57472(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
+; CHECK-NEXT: [[REM:%.*]] = srem i32 [[X]], 16
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[REM]], i32 42
+; CHECK-NEXT: ret i32 [[COND]]
+;
+entry:
+ %x.addr = alloca i32, align 4
+ store i32 %x, ptr %x.addr, align 4
+ %0 = load i32, ptr %x.addr, align 4
+ %cmp = icmp sge i32 %0, 0
+ br i1 %cmp, label %cond.true, label %cond.false
+
+cond.true:
+ %1 = load i32, ptr %x.addr, align 4
+ %rem = srem i32 %1, 16
+ br label %cond.end
+
+cond.false:
+ br label %cond.end
+
+cond.end:
+ %cond = phi i32 [ %rem, %cond.true ], [ 42, %cond.false ]
+ ret i32 %cond
+}
diff --git a/llvm/test/Transforms/SCCP/divrem.ll b/llvm/test/Transforms/SCCP/divrem.ll
new file mode 100644
index 0000000000000..6b85238050f0b
--- /dev/null
+++ b/llvm/test/Transforms/SCCP/divrem.ll
@@ -0,0 +1,198 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -passes=ipsccp -S < %s | FileCheck %s
+
+define i8 @sdiv_nonneg0_nonneg1(i8 %x, i8 %y) {
+; CHECK-LABEL: @sdiv_nonneg0_nonneg1(
+; CHECK-NEXT: [[PX:%.*]] = and i8 [[X:%.*]], 127
+; CHECK-NEXT: [[PY:%.*]] = lshr i8 [[Y:%.*]], 1
+; CHECK-NEXT: [[R:%.*]] = sdiv i8 [[PX]], [[PY]]
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %px = and i8 %x, 127
+ %py = lshr i8 %y, 1
+ %r = sdiv i8 %px, %py
+ ret i8 %r
+}
+
+define i8 @sdiv_nonnegconst0_nonneg1(i7 %y) {
+; CHECK-LABEL: @sdiv_nonnegconst0_nonneg1(
+; CHECK-NEXT: [[PY:%.*]] = zext i7 [[Y:%.*]] to i8
+; CHECK-NEXT: [[R:%.*]] = sdiv i8 42, [[PY]]
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %py = zext i7 %y to i8
+ %r = sdiv i8 42, %py
+ ret i8 %r
+}
+
+define i8 @sdiv_nonneg0_nonnegconst1(i8 %x) {
+; CHECK-LABEL: @sdiv_nonneg0_nonnegconst1(
+; CHECK-NEXT: [[PX:%.*]] = mul nsw i8 [[X:%.*]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = sdiv i8 [[PX]], 42
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %px = mul nsw i8 %x, %x
+ %r = sdiv i8 %px, 42
+ ret i8 %r
+}
+
+define i8 @sdiv_unknown0_nonneg1(i8 %x, i8 %y) {
+; CHECK-LABEL: @sdiv_unknown0_nonneg1(
+; CHECK-NEXT: [[PY:%.*]] = lshr i8 [[Y:%.*]], 1
+; CHECK-NEXT: [[R:%.*]] = sdiv i8 [[X:%.*]], [[PY]]
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %py = lshr i8 %y, 1
+ %r = sdiv i8 %x, %py
+ ret i8 %r
+}
+
+define i8 @sdiv_nonnegconst0_unknown1(i7 %y) {
+; CHECK-LABEL: @sdiv_nonnegconst0_unknown1(
+; CHECK-NEXT: [[SY:%.*]] = sext i7 [[Y:%.*]] to i8
+; CHECK-NEXT: [[R:%.*]] = sdiv i8 42, [[SY]]
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %sy = sext i7 %y to i8
+ %r = sdiv i8 42, %sy
+ ret i8 %r
+}
+
+define i8 @sdiv_unknown0_nonnegconst1(i8 %x) {
+; CHECK-LABEL: @sdiv_unknown0_nonnegconst1(
+; CHECK-NEXT: [[SX:%.*]] = mul i8 [[X:%.*]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = sdiv i8 [[SX]], 42
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %sx = mul i8 %x, %x
+ %r = sdiv i8 %sx, 42
+ ret i8 %r
+}
+
+define i8 @srem_nonneg0_nonneg1(i8 %x, i8 %y) {
+; CHECK-LABEL: @srem_nonneg0_nonneg1(
+; CHECK-NEXT: [[PX:%.*]] = and i8 [[X:%.*]], 127
+; CHECK-NEXT: [[PY:%.*]] = lshr i8 [[Y:%.*]], 1
+; CHECK-NEXT: [[R:%.*]] = srem i8 [[PX]], [[PY]]
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %px = and i8 %x, 127
+ %py = lshr i8 %y, 1
+ %r = srem i8 %px, %py
+ ret i8 %r
+}
+
+define i8 @srem_nonnegconst0_nonneg1(i8 %y) {
+; CHECK-LABEL: @srem_nonnegconst0_nonneg1(
+; CHECK-NEXT: [[PY:%.*]] = and i8 [[Y:%.*]], 127
+; CHECK-NEXT: [[R:%.*]] = srem i8 42, [[PY]]
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %py = and i8 %y, 127
+ %r = srem i8 42, %py
+ ret i8 %r
+}
+
+define i8 @srem_nonneg0_nonnegconst1(i7 %x) {
+; CHECK-LABEL: @srem_nonneg0_nonnegconst1(
+; CHECK-NEXT: [[PX:%.*]] = zext i7 [[X:%.*]] to i8
+; CHECK-NEXT: [[R:%.*]] = srem i8 [[PX]], 42
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %px = zext i7 %x to i8
+ %r = srem i8 %px, 42
+ ret i8 %r
+}
+
+define i8 @srem_unknown0_nonneg1(i8 %x, i8 %y) {
+; CHECK-LABEL: @srem_unknown0_nonneg1(
+; CHECK-NEXT: [[PY:%.*]] = lshr i8 [[Y:%.*]], 1
+; CHECK-NEXT: [[R:%.*]] = srem i8 [[X:%.*]], [[PY]]
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %py = lshr i8 %y, 1
+ %r = srem i8 %x, %py
+ ret i8 %r
+}
+
+define i8 @srem_nonnegconst0_unknown1(i7 %y) {
+; CHECK-LABEL: @srem_nonnegconst0_unknown1(
+; CHECK-NEXT: [[SY:%.*]] = sext i7 [[Y:%.*]] to i8
+; CHECK-NEXT: [[R:%.*]] = srem i8 42, [[SY]]
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %sy = sext i7 %y to i8
+ %r = srem i8 42, %sy
+ ret i8 %r
+}
+
+define i8 @srem_unknown0_nonnegconst1(i8 %x) {
+; CHECK-LABEL: @srem_unknown0_nonnegconst1(
+; CHECK-NEXT: [[SX:%.*]] = mul i8 [[X:%.*]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = srem i8 [[SX]], 42
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %sx = mul i8 %x, %x
+ %r = srem i8 %sx, 42
+ ret i8 %r
+}
+
+define i32 @PR57472(i32 %x) {
+; CHECK-LABEL: @PR57472(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X:%.*]], 0
+; CHECK-NEXT: br i1 [[CMP]], label [[T:%.*]], label [[F:%.*]]
+; CHECK: t:
+; CHECK-NEXT: [[REM:%.*]] = srem i32 [[X]], 16
+; CHECK-NEXT: br label [[EXIT:%.*]]
+; CHECK: f:
+; CHECK-NEXT: br label [[EXIT]]
+; CHECK: exit:
+; CHECK-NEXT: [[COND:%.*]] = phi i32 [ [[REM]], [[T]] ], [ 42, [[F]] ]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+entry:
+ %cmp = icmp sge i32 %x, 0
+ br i1 %cmp, label %t, label %f
+
+t:
+ %rem = srem i32 %x, 16
+ br label %exit
+
+f:
+ br label %exit
+
+exit:
+ %cond = phi i32 [ %rem, %t ], [ 42, %f ]
+ ret i32 %cond
+}
+
+define i32 @PR57472_alt(i32 %x) {
+; CHECK-LABEL: @PR57472_alt(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], 2000000000
+; CHECK-NEXT: br i1 [[CMP]], label [[T:%.*]], label [[F:%.*]]
+; CHECK: t:
+; CHECK-NEXT: br label [[EXIT:%.*]]
+; CHECK: f:
+; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 16, [[X]]
+; CHECK-NEXT: br label [[EXIT]]
+; CHECK: exit:
+; CHECK-NEXT: [[COND:%.*]] = phi i32 [ -42, [[T]] ], [ [[DIV]], [[F]] ]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+entry:
+ %cmp = icmp ugt i32 %x, 2000000000
+ br i1 %cmp, label %t, label %f
+
+t:
+ br label %exit
+
+f:
+ %div = sdiv i32 16, %x
+ br label %exit
+
+exit:
+ %cond = phi i32 [ -42, %t ], [ %div, %f ]
+ ret i32 %cond
+}
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